H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Document Table of Contents

4.3.1. TX PCS and RX PCS Datapath

Each H-Tile Hard IP for Ethernet IP instance contains a full featured multi-lane PCS layer, which offers a number of interfacing options from the FPGA fabric.
Figure 16. TX PCS Datapath

In FlexE mode, the TX Encoder in the PCS is bypassed; in OTN mode, both the TX Encoder and Scrambler are bypassed.

  • TX PCS encoder: Enables the data to be written in encoded form from the PCS66 interface.

  • TX PCS scrambler: Enables the data to be scrambled. Channels will not lock correctly if the data is not scrambled.
    Note: In OTN mode, scrambler is bypassed because the input data is expected to be scrambled.
  • Alignment insertion: The TX PCS interface inserts alignment markers
  • Striper: Enables logically sequential data to be segmented to increase data throughput.
Figure 17. RX PCS Datapath

In FlexE mode, RX data is aligned and descrambled, but not decoded; in OTN mode, it is only aligned.

In both modes, data are not decoded as the incoming data is not encoded.

  • Aligner: Enables the alignment of incoming data.
  • RX PCS descrambler: Enables the incoming scrambled data to be descrambled.
    Note: In OTN mode, descrambler is bypassed.
  • RX PCS decoder: Enables the incoming encoded data to be written in decoded form from the PCS66 interface.