DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023

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7.15.10. Super-sample NCO

This design example uses the NCO block from the Waveform Synthesis library to implement a super-sample NCO. The design demonstrates run-time reconfiguring of the frequency using a register bus.

A super-sample NCO uses multiple NCOs that each have an initial phase offset. When you combine the parallel outputs into a serial stream, they can describe frequencies N times the Nyquist frequency of a single NCO. N is the total number of NCOs that the design uses.

The NCO block in this design example produces four outputs. All outputs have the same phase increment but each have a different, evenly distributed initial phase offset. With the four parallel outputs in series they describe frequencies up to four times higher than the Nyquist frequency of an individual NCO.

To change the frequency of the super-sample NCO using the bus, write a new phase increment and offset to each of the four constituent NCOs and then strobe the synchronization register. The NCO block includes the phase increment register; a separate primitive subsystem implements the phase offset and synchronization registers.

The setup_demo_nco_super_sample scripts allows you to configure the clock rate, number of NCOs, NCO accumulator size, and many other parameters. This script calculates the required phase increment and offsets required to sweep the super-sample NCO through five frequencies. The script defines the memory map and creates the bus stimulus.

DSP Builder writes the output of the super-sample NCO into a MATLAB workspace variable and compares it with a MATLAB-generated waveform in the script test_demo_nco_super_sample.

DSP Builder schedules the bus in HDL but not in Simulink, so bus writes occur at different clock cycles. Therefore, the function verify_demo_nco_super_sample function verifies the design, which checks that the Simulink and ModelSim frequency distributions match within a tolerance.

The output of the Spectrum Analyser block show the simulation initializes to the last frequency in dspb_super_nco.frequencies and then rotates through the list.

The model file is demo_nco_super_sample.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.