DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023
Document Table of Contents

3.8. Simulating, Verifying, Generating, and Compiling Your DSP Builder Design

Before you begin:
  • Create a design
  • Check your design for errors


  1. In Simulink, click Simulate > Run.
    Note: Simulink generates the HDL then starts the simulation
  2. Analyze the simulation results.
  3. Verify generated hardware (optional).
    1. Click DSP Builder Verify Design.
    2. Turn on Verify at subsystem level, turn off Run Quartus Prime Software, and click Run Verification.
      Note: If you turn on Run Quartus Prime Software, the verification script also compiles the design in the Quartus Prime software. MATLAB reports the postcompilation resource usage details in the verification window.
      MATLAB verifies that the Simulink simulation results match a simulation of the generated HDL in the ModelSim simulator.
    3. Close both verification windows when MATLAB completes the verification.
  4. Examine the generated resource summaries:
    1. Click Simulate > Start.
    2. Click Resource Usage > Design for a top-level design summary.
  5. View the Avalon memory-mapped register memory map:
    1. Click Simulate > Start.
    2. Click Memory Map > Design. DSP Builder highlights in red any memory conflicts.
      Note: DSP Builder also generates the memory map in the <design name> _mmap.h file.
  6. Compile your design in the Quartus Prime software by clicking Run Quartus Prime. When the Quartus Prime software opens, click Processing > Start Compilation.

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