The FIFO block wraps the Intel single clock FIFO (SCFIFO) megafunction operating in show-ahead mode. That is, the read input, r, is a read acknowledgement which means the DSP Builder has read the output data, q, from the FIFO buffer, so you can delete it and show the next data output on q. The data you present on q is only valid if the output valid signal, v, is high
|FIFO Setup|| A vector of three non-zero integers in the format: [<depth> <fill_threshold> <full_period>]
If the inputs w or r is a vector, the FIFO setup parameter must be a three column matrix with the number of rows equal to the number of components in the vector. Each row in the matrix independently configures the depth, fill_threshold, and full_period of the FIFO buffer for the corresponding vector component.
|Signal||Direction||Type||Description||Vector Data Support||Complex Data Support|
You can to set fill_threshold to a low number (<3) and arrive at a state such that output t is high and output v is low, because of differences in latency across different pairs of ports—from w to v is 3 cycles, from r to t is 1 cycle, from w to t is 1 cycle. If this situation arises, do not send a read acknowledgement to the FIFO buffer. Ensure that when the v output is low, the r input is also low, otherwise a warning appears in the MATLAB command window. If the read acknowledgement is derived from a feedback from the t output, ensure that the fill_threshold is set to a sufficiently high number (3 or above). Likewise for the f output and the full_period.
You may supply vector data to the d input, and vector data on the q output is the result.