7.13.2. Automatic Gain Control
This design example shows a complex loop with several subloops that it schedules and pipelines without inserting registers. The design example spreads a lumped delay around the circuit to satisfy timing while maintaining correctness. Processor visible registers control the thresholds and gains.
In complex algorithmic circuits, the zero-latency blocks make it easy to follow a data value through the circuit and investigate the algorithm without offsetting all the results by the pipelining delays.
The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks.
The AGC_Chip subsystem includes the Device block, a RegField block and a lower level AGC subsystem.
The AGC subsystem includes RegField, ChannelIn, ChannelOut, Mult, SampleDelay, Add, Sub, Convert, Abs, CmpGE, Lut, Const, SharedMem, Shift, BitExtract, Select, and SynthesisInfo blocks.
The model file is demo_agc.mdl.