9.6.3. Implicit Delays in DSP Builder Designs
If the valid input drives directly the valid output, the delay on the valid signal matches the latency displayed on the ChannelOut block. It doesn't, if the valid output is generated in any other way, for example by using a Sequence block.
For example, the 4K FFT design example uses a Sequence block to drive the valid signal explicitly.
The latency that the ChannelOut block reports is therefore not 4096 + the automatic pipelining value, but just the pipelining value.