DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023
Public

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7.12.1. 16-Channel DDC

This design example shows how to use using IP and Interface blocks to build a 16-channel digital-down converter for modern radio systems.

Decimating CIC and FIR filters down convert eight complex carriers (16 real channels) from 61.44 MHz. The total decimation rate is 64. A real mixer and NCO isolate the eight carriers. The testbench isolates two channels of data from the TDM signals using a channel viewer.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus a ChanView block that deserializes the output bus. An Edit Params block allows easy access to the setup variables in the setup_demo_ddc.m script.

The DDCChip subsystem includes Device, Decimating FIR, DecimatingCIC, Mixer, NCO, Scale, RegBit, and RegField blocks.

The model file is demo_ddc.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.