2.2. DSP Builder for Intel® FPGAs Design Structure
The Top-Level Design
A DSP Builder advanced blockset top-level design consists of:
- A Simulink testbench, which provides design inputs and allows you to analyze inputs and outputs
- Top-level configuration blocks
- Optional memory interface specification and stimulus blocks.
- External Memory block to configure an external memory interface
- BusStimulus and BusStimulusFileReader blocks to stimulate Avalon-MM interfaces during simulation
- Edit Params block as a shortcut to opening a script setup_<model name>.m for editing.
The top-level design must have a Control block to specify RTL output directory and top-level threshold parameters
The Synthesizable Top-Level Design
The synthesizable top-level design is a Simulink subsystem that contains a Device block, which sets which family, part, and speed grade to target. The synthesizable top-level design is at the top level of the generated hardware files. The synthesizable top-level design can consist of further level of hierarchies that include primitive subsystems.
Optionally, you can include more LocalThreshold blocks to override threshold settings defined higher up the hierarchy.
The Primitive Subsystem
Primitive subsystems are scheduled domains for Primitive and IP library blocks. A primitive subsystem must have:
- A SynthesisInfo block, with synthesis style set to Scheduled, so that DSP Builder can pipeline and redistribute memories optimally to achieve the desired clock frequency.
- Boundary blocks that delimit the primitive subsystem:
- ChannelIn (channelized input),
- ChannelOut (channelized output),
- GPIn (general purpose input)
- GPOut (general purpose output).
DSP Builder synchronizes connections that pass through the same boundary block.
Use system interface blocks to delimit the boundaries of scheduled domains within a subsystem. Within these boundary blocks DSP Builder optimizes the implementation you specify by the schematic. DSP Builder inserts pipelining registers to achieve the specified system clock rate. When DSP Builder inserts pipelining registers, it adds equivalent latency to parallel signals that need to be kept synchronous so that DSP Builder schedules them together. DSP Builder schedules signals that go through the same input boundary block (ChannelIn or GPIn) to start at the same point in time; signals that go through the same output boundary block (ChannelOut or GPOut) to finish at the same point in time. DSP Builder adds any pipelining latency that you add to achieve fMAX in balanced cuts through the signals across the design. DSP Builder applies the correction to the simulation at the boundary blocks to account for this latency in HDL generation. The primitive subsystem as a whole remains cycle accurate. You can specify further levels of hierarchy within primitive subsystems containing primitive blocks, but no further primitive boundary blocks or IP blocks.
Use SampleDelay blocks only to specify relative sample offsets of data-streams; do not use for pipelining.