DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023
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15.6.9. Reset-Priority Latch (SRlatch_PS)

DSP Builder offers two single-cycle latency latch subsystems for common operations for the valid signal, latching with set and reset. The SRlatch block gives priority to the reset input signal; the SRlatch_PS block gives priority to the set input signal. In both blocks, if set and reset inputs are both zero the current output state is maintained.
Table 272.  Truth Table for SRlatch_PS
S R Q
0 0 Q
1 0 1
0 1 0
1 1 0