DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023

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9.6.5. Latency and fMAX Constraint Conflicts in DSP Builder Designs

Some blocks need to have a minimum latency, either because of logical or silicon limitations. In these cases, you can create an abstracted design that cannot be realized in hardware. While these cases can generally be addressed, in some cases like IIRs, find algorithmic alternatives.

Generally, problems occur in feedback loops. You can solve these issues by lowering the fMAX target, or by restructuring the feedback loop to reduce the combinatorial logic or increasing the delay. You can redesign some control structures that have feedback loops to make them completely feed forward.

You cannot set a latency constraint that conflicts with the constraint that the fMAX target implies. For example, a latency constraint of < 2 may conflict with the fMAX implied pipelining constraint. The multiplier may need four pipelining stages to reach the target fMAX. The simulation fails and issues an error, highlighting the Primitive subsystem.

DSP Builder gives this error because you must increase the constraint limit by at least 3 (that is, to < 5) to meet the target fMAX.