7.4.3. Decimating FIR Filter
This design example uses the Decimating FIR block to build a 20-channel decimate by 5, 49-tap FIR filter with a target system clock frequency of 240 MHz.
The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_fird.m script.
The FilterSystem subsystem includes the Device and Decimating FIR blocks.
The model file is demo_fird.mdl.