188.8.131.52. FIR Filter Avalon-MM Interfaces
- To allow read, write, or readwrite access to coefficients from system bus interfaces, select Read, Write, or Readwrite for the FIR block Bus mode. Select Constant to disable this interface.
- Specify the bus address width and data type on the FIR block and on the Avalon memory-mapped Settings block. FIR blocks automatically generate the appropriate bus logic and interface for your design.
- To place the bus logic on a separate clock domain specify Separate bus clock in the Avalon memory-mapped Settings block.
- DSP Builder hides the agent interface ports by default in the simulation model. Use the BusStimulus block to access this interface during simulation (similar to Interface blocks). Use the base address specified on the FIR block for accessing the coefficients.
- In generated RTL, DSP Builder adds these ports to FIR blocks and routes them to the Avalon memory-mapped agent interface. Set the width of data and address ports (Avalon Data and Address Width) in the Avalon memory-mapped Settings block.
In your higher level system, access FIR coefficients through the agent interface at the base address you specified on the FIR block.
When you expose bus interface ports in the Simulink design (turn on Expose Bus Interface), a valid sub-set of Avalon memory-mapped agent interface ports appears on the block based on the selected bus mode. You can now make direct connections to these ports in the Simulink model for accessing the coefficients. The FIR coefficient width sets the data ports (write and read). DSP Builder places bus agent logic on the system clock domain.
Address of the request. DSP Builder adds address to your design when Bus Mode is not set to Constant.
The port width depends on the Bus Address Width in the Avalon Memory-Mapped Settings block.
For the first coefficient use the Base Address you specify for the block and for the last one use: Base Address + Number Of Coefficients -1
The port width depends on the coefficient width of the FIR block.
Set data and address and assert write port simultaneously to initiate a write request.
Set the address to a valid address and assert this single-bit input simultaneously every time you want to initiate a read request.
After sending a read request, wait for valid to be asserted indicating that read data is available on readdata.
You don’t need to wait for the completion of the first read request to initiate a second read request. The agent supports pipelined reads. DSP Builder provides the responses in the exact same order you send the read requests.
Assert this single-bit input every time you need to initiate a write request.
Do not assert read and write ports at the same time, otherwise, you see undefined behavior.
DSP Builder sets the port width the same as the FIR coefficient width. This output provides data for read responses.
Only capture this output if you assert valid output.
Read data valid.
This single-bit output indicates that valid data is available on readdata.