22.214.171.124. NCO Block Phase Increment Memory Registers
The NCO block only supports one or two registers for each phase increment value. If one register is required for each phase increment value, the phase increment value for the first frequency is written into the base address, the second value into the next address (base address + 1) and so on. If you require two registers, the design uses the base address and the next address (base address + 1) for the first value with each address storing part of the value. The next pair of addresses store the next value and so on.
For example, for a System Data Width of 16, Accumulator Bit Width of 24 and Phase Increment and Inversion Memory Map base address of 1000, addresses 1000 and 1001 store the phase increment value for the first frequency. Address 1001 stores the lower 16 bits (15 .. 0) and address 1000 stores the remaining 8 bits (23 .. 16). If DSP Builder generates four channels of sinusoidal signals, it uses addresses 1002 and 1003 for the second channel, addresses 1004 and 1005 for the third channel, addresses 1006 and 1007 for the fourth channel.
<total addresses required> = <number of registers per value> × <number of channels>
When DSP Builder writes to the phase increment and inversion memory map registers (in write mode), the new value takes effect immediately.
If the application is a super-rate operation (like direct RF DUC) and multiple channels in the NCO are configured for a new center frequency, first configure the phase increment value for each channel. DSP Builder then synchronizes the phase offsets of all channels at the same time by asserting the sync pulse.
To minimize the duration of disruption, you may use two banks of phase increment registers. The new phase increment registers bank switches first. Then, you can apply the sync pulse to synchronize the new phase offsets.