DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

4.1.2.1. DSP Builder Block Interface Signals

DSP Builder designs have three basic interface signals: valid, channel, and data.

The channel (uint8) signal is a synchronization counter for multiple channel data on the data signals. Typically, it increments from 0 with the changing channels across the data signals within a frame of data

The data signals can be any number of synchronized signals carrying single or multichannel data.

The valid (ufix(1) or bool)) signal indicates whether the concurrent data and channel signals have valid information (1), are unknown (0), or do not care (0).

DSP Builder uses these three synchronized signals, to internally connect IP or synthesized subsystems and externally connect upstream and downstream blocks. Thus these three signals connect most of the blocks in a DSP Builder advanced blockset design.

Only one set of valid, channel,and data signals can exist in a IP and synthesized subsystem. But multiple data signals can exist in a customized synthesizable subsystem.

Data on the data wire is only valid when DSP Builder asserts valid high. During this clock cycle, channel carries an 8-bit integer channel identifier. DSP Builder preserves this channel identifier through the datapath, so that you can easily track and decode data.

This simple protocol is easy to interface with external circuitry. It avoids balancing delays, and counting cycles, because you can simply decode the valid and channel signals to determine when to capture the data in any downstream blocks. DSP Builder distributes the control structures in each block of your design.

In Primitive subsystems, DSP Builder guarantees all signals that connect to ChannelOut blocks line up in the same clock cycle. That is, the delays balance on all paths from and to these blocks. However, you must ensure all the signals arrive at a ChannelIn block in the same clock cycle.

The IP library blocks follow the same rules. Therefore, it is easy to connect IP blocks and Primitive subsystems.

The IP library filters all use the same protocol with an additional simplification—DSP Builder produces all the channels for a frame in a multichannel filter in adjacent cycles, which is also a requirement on the filter inputs. If a FIR filter needs to use flow control, pull down the valid signal between frames of data—just before you transmit channel 0 data.

The same <data, valid, channel> protocol connects all CIC and FIR filter blocks and all subsystems with Primitive library blocks. The blocks in the Channel Filter and Waveform library support separate real and imaginary (or sine and cosine) signals. The design may require some splitting or combining logic when using the mixer blocks. Use a Primitive subsystem to implement this logic.