DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023
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15.3.19. Single-Wire Transpose (Transpose)

The DSP Builder Transpose block performs a specialized reordering of a block of data.The size of the block must be a power of 2.

You specify the reordering as an arbitrary permutation of the address bits. The block numbers the address bits from 0 (least significant). The block specifies the permutation by listing the address bits in order, starting with the least significant.

For example, specifying:

[5 4 3 2 1 0] bit-reverses a block of 64 elements

[4 5 2 3 0 1] digit-reverse it (radix 4)

[0 1 2 3 4 5] leaves the order of the data unchanged

[4 5 0 1 2 3] interleaves four blocks of 16 elements each

[2 3 4 5 0 1] deinterleaves four blocks of 16 elements

Table 137.  Parameters for the Transpose Block
Parameter Description
Address permutation A vector of integers that describes how to rearrange the block of data.
Table 138.  Port Interface for the Transpose Block
Signal Direction Type Description
v Input Boolean. Input valid signal.
d Input Any type. Data input.
qv Output Boolean. Output valid signal.
q Output Same as d Data output.
g Output Boolean, Start of output block.