7.14.7. 4-Carrier, 2-Antenna W-CDMA DUC
The top-level testbench includes Control, Signals, and Run Quartus Prime blocks. A Spectrum Scope block computes and displays the periodogram of the outputs from the two antennas.
The DUCChip subsystem includes a Device block to specify the target FPGA device, and a DUC subsystem that contains InterpolatingFIR, InterpolatingCIC, NCO, ComplexMixer, and Scale blocks.
The FIR and CIC filters implement an interpolating filter chain that up converts the 16-channel input data from a frequency of 3.84 MSPS to a frequency of 122.88 MSPS (a total interpolation factor of 32). The complex mixer and NCO modulate the four channel baseband input signal onto the IF region. The design configures the NCO with four channels to provide four pairs of sine and cosine waves at frequencies of 12.5 MHz, 17.5 MHz, 22.5 MHz, and 27.5 MHz, respectively. The NCO has the same sample rate (122.88 MSPS) as the final interpolated output sample rate from the last CIC filter in the interpolating filter chain.
The subsystem SyncMixSumSel uses Primitive blocks to implement the synchronization, mixing, summation, scaling, and signal selection. This subsystem separates each operation into further subsystems. The Sync subsystem shows how to manage two data streams that come together and synchronize. The data from the NCOs writes to a memory with the channel as an address. The data stream uses its channel signals to read out the NCO signals, which resynchronizes the data correctly.
The Sum and SampSelectr subsystems sum up the correct modulated signals to the designated antenna.
A system clock rate of 245.76 MHz drives the design on the FPGA, which the Device block defines inside the DUC subsystem.
The model file is wcdma_multichannel_duc_mixer.mdl.