DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook
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4.7.1. DSP Builder Generated Files
File | Description |
---|---|
rtl directory | |
<model name>.xml | An XML file that describes the attributes of your model. |
<model name>_entity.xml | An XML file that describes the boundaries of the system. |
<model name>_params.xml | When you open a model, DSP Builder produces a model_name_params.xml file that contains settings for the model. You must keep this file with the model. |
rtl/<model name> subdirectory | |
<block name>.xml | An XML file containing information about each block in the advanced blockset, which translates into HTML on demand for display in the MATLAB Help viewer and for use by the DSP Builder menu options. |
<model name>.vhd | This is the top-level testbench file. It may contain non-synthesizable blocks, and may also contain empty black boxes for Simulink blocks that are not fully supported. |
<model name>.add.tcl | This script loads the VHDL files in this subdirectory and in the subsystem hierarchy below it into the Quartus Prime project. |
<model name>.qip | This file contains information about all the files DSP Builder requires to process your design in the Quartus Prime software. The file includes a reference to any .qip file in the next level of the subsystem hierarchy. |
<model name>_<block name>.vhd | DSP Builder generates a VHDL file for each component in your model. |
<model name>_<subsystem>_entity.xml | An XML file that describes the boundaries of a subsystem as a black-box design. |
<subsystem>.xml | An XML file that describes the attributes of a subsystem. |
*.stm | Stimulus files. |
safe_path.vhd | Helper function that the .qip and .add.tcl files reference to ensure that pathnames read correctly in the Quartus Prime software. |
safe_path_msim.vhd | Helper function that ensures a path name reads correctly in ModelSim. |
<subsystem>_atb.do | Script that loads the subsystem automatic testbench into ModelSim. |
<subsystem>_atb.wav.do | Script that loads signals for the subsystem automatic testbench into ModelSim. |
<subsystem>/<block>/*.hex | Files that initialize the RAM in your design for either simulation or synthesis. |
<subsystem>.sdc | Design constraint file for timing analyzer support. |
<subsystem>.tcl | This Tcl script exists only in the subsystem that contains a Device block. You can use this script to setup the Quartus Prime project. |
<subsystem>_hw.tcl | A Tcl script that loads the generated hardware into Platform Designer. |