DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

15.3.24. Twiddle Generator (TwiddleGenC) Deprecated

The TwiddleGenC block generates the appropriate complex coefficients that multiplies the streaming data in a radix-22 streaming FFT or iFFT architecture.

Feed at the input by a modulo N counter (where N is an integer power of two) and the appropriate complex sequence generates at the output.

To parameterize this block, set the Counter bit width parameter with log2(N) and enter the width in bits and fixed-point scaling of the twiddle factors. A cosine or sine wave has a range of [-1:1], therefore you must provide at least two integer bits, and as many fractional bits as are appropriate. Starting with a twiddle bit width of 16 bits (enter 16 as the twiddle bit width), and a scaling of 2–14 (enter 14 as the Twiddle scaling exponent). The resulting fixed-point type is sfix16_en14 (2.14 fixed-point format).

Table 145.  Parameters for the TwiddleGenC Block
Parameter Description
FFT type Specifies whether to generate twiddle factors for an FFT or an IFFT.
Counter bit width Specifies the counter width in bits.
Twiddle bit width Specifies the twiddle width in bits.
Twiddle scaling exponent value Specifies the fixed-point scaling factor of the complex twiddle factor.
Table 146.  Port Interface for the TwiddleGenC Block
Signal Direction Type Description
counter Input Any fixed-point type Counter signal.
w Output Derived complex fixed-point type Complex data output.