DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023
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7.14.4. 2-Antenna WiMAX DUC

This reference design uses IP, Interface, and Primitivelibrary blocks to build a 4-channel, 2-antenna, single-frequency modulation DUC for use in an IF modem design compatible with the WiMAX standard.

The top-level testbench includes Control, Signals, and Run Quartus Prime blocks. The design includes an Edit Params block to allow easy access to the setup variables in the setup_wimax_duc_2tx_iiqq.m script.

The DUCChip subsystem includes a Device block to specify the target FPGA device, and a DUC2Channel subsystem which contains SingleRateFIR, Scale, InterpolatingFIR, NCO, ComplexMixer, and Const blocks. It also contains a Sync subsystem, which shows how to manage two data streams coming together and synchronizing. The design writes the data from the NCOs to a memory with the channel index as an address. The data stream uses its channel signals to read out the NCO signals, which resynchronizes the data correctly. (Alternatively, you can simply delay the NCO value by the correct number of cycles to ensure that the NCO and channel data arrive at the Mixer on the same cycle). The deinterleaver subsystem contains a series of Primitive blocks including delays and multiplexers that de-interleave the four I and Q channels.

The FIR filters implement an interpolating filter chain that up converts the two channels from a frequency of 11.2 MSPS to a frequency of 89.6 MSPS (a total interpolating rate of 8).

A complex mixer and NCO modulate the two input channel baseband signals to the IF domain. The design configures the NCO to provide two sets of sine and cosine waves at a frequency of 22.4 MHz. The NCO has the same sample rate (89.6 MSPS) as the input data sample rate.

The Sync subsystem shows how to manage two data streams coming together and synchronizing. The design writes the data from the NCOs to a memory with the channel as an address. The data stream uses its channel signals to read out the NCO signals, which resynchronizes the data correctly.

A system clock rate of 179.2 MHz drives the design on the FPGA, which the Device block defines inside the DUCChip subsystem.

The model file is wimax_duc_2tx_iiqq.mdl.

Note: This reference design uses the Simulink Signal Processing Blockset.