7.13.8. Fibonacci Series
This design example shows that even for circuitry with tight feedback loops and 120-bit adders, designs can achieve high data rates by the pipelining algorithms. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks. The Chip subsystem includes the Device block and a lower level FibSystem subsystem. The FibSystem subsystem includes ChannelIn, ChannelOut, SampleDelay, Add, Mux, and SynthesisInfo blocks.
The model file is demo_fibonacci.mdl.