DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023

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12.1. Avalon Memory-Mapped Agent Settings (AvalonMemoryMappedAgentSettings)

The AvalonMemoryMappedAgentSettings block specifies information about the top-level memory-mapped bus interface widths.
Note: You can either use this block in your design or view the Avalon-MM agent interface settings on the DSP Builder > Avalon Interface menu.
Table 27.  Parameters for the AvalonMemoryMappedAgentSettings Block
Parameter Description
Bus interface name Specifies the prefix for the address, data and control signals in the generated control bus.
Address width Specifies the width in bits of the memory-mapped address bus (1–32, default=10).
Data width Specifies the width in bits of the memory-mapped data bus (16, 32, or 64, default=16). DSP Builder does not support byte enables for Avalon memory-mapped agent interface. Only connect hosts to this interface that have the same or a smaller data width. For example, to attach a JTAG host, set the data width to 32 bits or less.

When using SharedMem block ensure the output data width matches the AvalonMemoryMappedAgentSettings bus data width or is exactly twice the bus data width.

Bus is: Specifies whether the memory-mapped address bus is Big Endian or Little Endian.
Separate bus clock Turn on so any processor-visible control registers are clocked by a separate control bus clock to ease timing closure.
Bus clock frequency (MHz) Specifies the frequency of the separate processor interface bus clock (when enabled).
Bus clock synchronous with system clock Turn on so the bus clock is synchronous with the system clock.

Word and Byte Addressing

Use word addressing when accessing memory-mapped blocks in DSP Builder from the design logic or through DSP Builder processor interface (using the BusStimuli block). Use byte addressing when you access the same locations through DSP Builder MATLAB API. To change the word address to byte address, multiply it by the number of bytes in AvalonMemoryMappedAgentSettings block data width. If you use the BusStimuliFileReader block to drive the BusStimulus block, ensure values for Data Width and Address Width parameters exactly match the address and data width you set in Avalon Interfaces > Avalon Memory-Mapped Settings

Note: Ensure your access permissions are correct, when using the RegBit, RegField, and SharedMemblocks from the Interface library.
Note: If you read from a nonreadable address, the output data is not valid.

When using the SharedMem block the output data width is twice the bus data width. In the DSP Builder processor interface, the block appears to have twice the number of entries compared with the design view. Also DSP Builder interprets each element in an initialization array to be of output data width. Use the System Console MATLAB API in DSP Builder to access the memory-mapped locations in DSP Builder designs on the FPGA. Use byte addressing when using this interface:

dspba_design_base_address_in_qsys + (block_address_in_dspba_design* dspba_bus_data_width_bytes)

Read and write requests time out in 1 minute if the device shows no response for the initiated request. For example:

  • Read or write requests to an address that is not assigned to any slave in the top-level system.
  • Read requests to a memory-mapped location that does not have read access (i.e. write only).

DSP Builder responds to read requests to non-readable or unassigned addresses with invalid data, because unanswered read requests may block the interconnect, so further valid requests don’t go through. DSP Builder accepts write requests, but ignores them if the address is non-writable.

If the subsequent requests to valid addresses and locations continue to time out, the initial request disables the bus interconnect. You must then reset the system or reprogram the board.

Additionally, close all your host connections in MATLAB before switching off or reprogramming the board, because MATLAB corrupts the existing connection. If you cannot start a new debugging session, restart MATLAB.

Clock Crossing

DSP Builder designs use a separate clock for all processor visible control registers if you select Separate bus clock in Avalon Interfaces > Avalon Memory-Mapped Settings. This clock is asynchronous to a main system clock if you turn off Bus clock synchronous with system clock.

DSP Builder inserts simple two-stage synchronizers between the bus and system clock domains. DSP Builder adds the synchronization to the autogenerated bus slave logic if you use any of the Interface blocks (e.g. RegField) and to NCO IP if you enable writable access to configuration registers inside the NCO.

The DSP Builder-generated timing constraints set maximum and minimum delays for paths between two different clocks to a big enough range, so timing analyzer doesn’t show an error. Using this method allows you to overwrite constraints for concrete paths if required. However, specifying a false path constraint takes precedence over other constraints.

You can use similar constraints for all such paths in DSP Builder blocks for the higher level projects.

When you add synchronizers to DSP Builder designs, the Quartus Prime timing analyzer also provides a metastability report.