DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/26/2023

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7.13.16. Matrix Initialization of LUT

This design example feeds a vector of addresses to the Primitive block such that DSP Builder gives each vector component a different address. This design example also shows Lut blocks working with complex data types. You can initialize Lut blocks in exactly the same way.

Using this design example avoids demultiplexing, connecting, and multiplexing, so that you can build parameterizable systems.

You can use one of the following ways to specify the contents of the Lut block:

  • Specify table contents as single row or column vector. The length of the 1D row or column vector determines the number of addressable entries in the table. If DSP Builder reads vector data from the table, all components of a given vector share the same value.
  • When a look-up table contains vector data, you can provide a matrix to specify the table contents. The number of rows in the matrix determines the number of addressable entries in the table. Each row specifies the vector contents of the corresponding table entry. The number of columns must match the vector length, otherwise DSP Builder issues an error.
Note: The default initialization of the LUT is a row vector round([0:255]/17). This vector is inconsistent with the default for the DualMem block, which is a column vector [zeros(16, 1)]. The latter form is consistent with the new matrix initialization form in which the number of rows determines the addressable size.

The model file is demo_lut_matrix_init.mdl.