AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents Power Pin Connections and Power Supplies

GUIDELINE: Follow the guidelines in the "Power Pin Connections and Power Supplies" section in the AN 738: Intel® Arria® 10 Device Design Guidelines.

Follow the guidelines for Intel® Arria® 10 SoC devices as documented in the "Arria 10 SX Pin Connection Guidelines" section of the Intel Arria 10 GX, GT and SX Device Family Pin Connection Guidelines.

GUIDELINE: Consider ramp times for maximum transient currents on supplies when designing the Power Distribution Network (PDN).

When using the PDN Tool to calculate the required target impedance of your application’s PDN for the core fabric’s VCC supply, model the ramp time of the maximum transient current on VCC using the Core Clock Frequency and Current Ramp Up Period parameters. This procedure relaxes the target impedance requirements relative to the default step function analysis, resulting in a more efficient PDN with fewer decoupling capacitors.

Initial transient current estimates can be obtained from the EPE Spreadsheet, and more accurate analysis is possible with the Power Analyzer Analysis Tool in Intel® Quartus® Prime when the design is closer to completion.

For more information, refer to the Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide.

GUIDELINE: Overdrive for maximum HPS MPU clock frequency.

Intel® Arria® 10 SoC devices support HPS MPU overclocking.

For the maximum achievable MPU frequency and the associated requirements on device speed grade and HPS supply overdrive levels, refer to the Intel Arria 10 Device Data Sheet.