AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

2.1. Overview of HPS Memory-Mapped Interfaces

The HPS exposes five Arm* Advanced Microcontroller Bus Architecture 3 ( AMBA* ) 3 Advanced eXtensible Interface (AXI*) memory mapped interfaces for memory transfers between the HPS and the FPGA fabric. Each port has a different purpose and associated direction.

The HPS component in Platform Designer can be connected to masters and slaves that implement Avalon® -MM interfaces or supported AMBA* 3 and 4 interfaces such as AMBA* 3 AXI and AMBA* 4 AXI4. Platform Designer generates an interconnect to handle interoperability between interfaces that have different capabilities or use different protocols.

Figure 1. Arria 10 HPS Connectivity