AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

1.2. Overview of HPS Design Guidelines for SoC FPGA design

Table 2.  HPS: Design Guidelines Overview

Stages of the HPS Design Flow



Hardware and Software Partitioning

Determine your system topology and use it as a starting point for your HPS to FPGA interface design

Guidelines for Interconnecting the Intel Arria 10 HPS and FPGA

HPS Pin Multiplexing and I/O Configuration Settings

Plan configuration settings for the HPS system including I/O multiplexing options, interface to FPGA and SDRAM, clocks, peripheral settings

Design Considerations for Connecting Device I/O to HPS Peripherals and Memory

HPS Clocks and Reset Considerations

HPS clocks and cold and warm reset considerations

HPS Clocking and Reset Design Considerations

HPS EMIF Considerations

Usage of the HPS EMIF controller and related considerations

HPS EMIF Design Considerations

FPGA Accelerator Design Considerations

Design considerations to manage coherency between FPGA accelerators and the HPS

DMA Considerations