AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

5.1.12. HPS ECC Design Considerations

ECC is implemented throughout the entire HPS on all RAMs, including the external HPS EMIF, L2 cache data RAMs and all peripheral RAMs. All HPS ECC controllers are based on an extended Hamming code algorithm, providing single-error correction and double-error detection (SECDED). Parity protection is provided for the Arm* Cortex-A9 MPCore* L1 cache memories and L2 tag RAM. ECC can be selectively enabled on the HPS EMIF and internal HPS RAMs. Diagnostic test modes and error injection capability are available under software control. ECC is disabled by default upon power-up or cold reset.

The generated boot code configures, initializes, and enables ECC according to user options selected during BSP generation. Custom firmware and bare metal application code access to the ECC features is facilitated with the Intel-provided HWLIBS library, which provides a simple API for programming HPS hardware features.

For more information, refer to "Boot Tools User Guide" and "Hardware Library" chapters in the SoC FPGA Embedded Development Suite User Guide.