AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents MPU Standby Modes and Dynamic Clock Gating

CPU standby modes and dynamic clock gating logic can be utilized throughout the MPU System Complex. Each CPU can be placed in standby mode, Wait for Interrupt, or Wait for Event mode to further minimize power consumption.

GUIDELINE: Refer to the Cortex-A9 Processor Power Control section in the Arm* Cortex-A9 Technical Reference Manual for more information on standby modes.

GUIDELINE: Utilize the power optimization examples available at the SoC Design Examples web page.

Please refer to the Arm* Cortex-A9 Technical Reference Manual and SoC Design Examples for more information regarding the above guidelines.