AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.3.4. Internal Clocks

Once you have validated the HPS clock configuration as described in the HPS Clock Configuration Planning guidelines, you must implement your HPS clock settings under software control, which is typically done by the boot loader software. You must also follow guidelines for transferring reference clocks between the HPS and FPGA.

GUIDELINE: Avoid cascading PLLs between the HPS and FPGA.

Cascading PLLs between the FPGA and HPS has not been characterized. Unless you perform a jitter analysis, do not chain the FPGA and HPS PLLs together. Output clocks from HPS are not intended to be fed into PLLs in the FPGA.

There are specific requirements for managing HPS PLLs and clocks under software control.

The boot loader software provided by SoC FPGA EDS meets all requirements for managing HPS PLLs and clocks. If you are developing your own boot loader software, see the related documentation.

Related Documentation

For more information, refer to the "Clock Manager" section and the specific peripheral and subsystem chapters in the Intel® Arria® 10 Hard Processor System Technical Reference Manual for the required software flow.

For more information about requirements specific to ramping HPS PLL frequencies to their final values, refer to the "Correct Sequence Required When Raising HPS PLL Frequency" chapter of the Intel® Arria® 10 SX Device Errata and Design Recommendations.