AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.4.1. Considerations for Connecting HPS to SDRAM

The hard memory controller for the Intel® Arria® 10 HPS is located in the FPGA I/O columns along with the other hardware memory controllers. The HPS can use only one hard memory controller bank, and it is located closest to the HPS block in I/O bank 2K, is where the address/command and ECC signals reside. Use I/O Bank 2J for 16-bit and 32-bit interface DQ/DQS data group signals. I/O Bank 2I, available only in the KF40 package, is used for 64-bit interface DQ/DQS data group signals for wider. Bank 2I is for the upper 32-bits of 64-bit interfaces.

Instantiating the Intel® Arria® 10 HPS EMIF IP

Connecting external SDRAM to the Intel® Arria® 10 HPS requires the use of an EMIF IP that is specific to the HPS. Follow the below guidelines for properly instantiating and configuring the correct EMIF IP for the HPS.

GUIDELINE: Instantiate the " Intel® Arria® 10 External Memory Interfaces for HPS" IP in Platform Designer.

You must use a specific EMIF IP in Platform Designer to connect the HPS to external SDRAM. This Platform Designer component is named “ Intel® Arria® 10 External Memory Interfaces for HPS” and can be found in the “IP Catalog” pane inPlatform Designer in the “Hard Processor Components” subgroup under the “Processors and Peripherals” group.

During compilation, Intel® Quartus® Prime uses the settings in this IP (memory type, width, timings and others) to generate the calibration algorithm for I/O AUX block. The code is executed during configuration of the device in order to set up and calibrate the HPS EMIF interface.

GUIDELINE: Connect the hps_emif conduit to the HPS component

The hard memory controller connected to the HPS has a dedicated connection that must be connected in Platform Designer. The Intel® Arria® 10 EMIF for HPS IP component exposes this connection through a conduit called hps_emif that must be connected to the HPS component’s “emif” conduit.

Figure 7. HPS Component Connected to the hps_emif

GUIDELINE: Make sure the HPS EMIF IP block is not reset while the HPS is accessing external SDRAM or resources in the L3 SDRAM Interconnect.

Asserting reset to the HPS EMIF IP block should coincide with the HPS reset assertion unless the application is capable of saving and recovering context in co-ordination with HPS EMIF IP reset assertion. This can be achieved by connecting the HPS EMIF reset input to one or a combination of resets from the following sources: HPS reset outputs (e.g. h2f_reset, h2f_cold_reset), other resets in the system that also source an HPS cold or warm reset input (e.g. HPS_nPOR, HPS_nRST, FPGA-to-HPS cold/warm reset requests).

If the HPS EMIF IP is reset without resetting the HPS as described above, the application must put the L3 SDRAM Interconnect in reset using the brgmodrst register, bit 6 (ddrsch) in the Reset Manager before HPS EMIF IP reset assertion and not release it until after the HPS EMIF IOPLL has locked. Failure to do so can result in locking up the processor on subsequent accesses to external SDRAM or resources in the L3 SDRAM Interconnect.

GUIDELINE: Ensure that the HPS memory controller Data Mask (DM) pins are enabled.

When you instantiate the memory controller in Platform Designer, you must select the checkbox to enable the data mask pins. If this control is not enabled, data corruption occurs any time a master accesses data in SDRAM that is smaller than the native word size of the memory.

GUIDELINE: Ensure that you choose only DDR3 or DDR4 components or modules in configurations that are supported by the Arria 10 EMIF for HPS IP and your specific device/package combination.

Intel® 's External Memory Interface Spec Estimator is a parametric tool that allows you to compare supported external memory interface types, configurations and maximum performance characteristics in Intel® FPGA and SoC devices.
Note: Not all device and package combinations support 64-/72-bit wide interfaces.

For more information about the External Memory Interface Spec Estimator, refer to the External Memory Interface web page on the Intel FPGA website.

For more information, refer to the "External Memory Interfaces in Arria 10 Devices" chapter in the Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook.