AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents Processor and Memory Clock Speeds

The biggest contribution to power consumption from the HPS is the processor clock speed and the type, size and speed of the external SDRAM program memory.

Careful selection of these system parameters to satisfy the functional and performance requirements of the application while not being over designed helps to minimize system power consumption.

GUIDELINE: Use the Intel® Arria® 10 FPGA-to-HPS bridge design example to tune HPS clock and memory interface parameters for your application's performance requirements.

The design example is delivered as a Platform Designer subsystem to allow performance-related parameters, including MPU clock speed, Interconnect speed, and memory type, configuration and speed.

Intel® Arria® 10 SoC development kits offer a selection of convenient hardware platforms for such analysis in the early stages of design. The Intel® Arria® 10 SoC Development Kit features high speed socketed external SDRAM memory daughter cards to experiment with different memory types and speeds.

With an optimal set of design parameters for the HPS and external SDRAM, your design will be optimized for lowest power consumption while still satisfying your application's performance requirements.

For more information, refer to the Intel® FPGA Boards web page, FPGA-to-HPS Bridges Design Example, and Intel® Arria® 10 SoC Development Kit links on the Intel website.