AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.3.1. HPS Clock Planning

HPS clock planning involves choosing clock sources and defining frequencies of operation for the following HPS components:
  • HPS PLLs
  • MPU System Complex
  • L3 Interconnect
  • HPS Peripherals
  • HPS-to-FPGA user clocks

HPS clock planning depends on system-level design planning in the areas of board-level clock planning, clock planning for the FPGA portion of the device, and HPS peripheral external interfacing. Therefore, it is important to validate your HPS clock configuration before finalizing your board design.

GUIDELINE: Verify the MPU and peripheral clocks using Platform Designer.

Use Platform Designer to initially define your HPS component configuration. Set the HPS input clocks, peripheral source clocks and frequencies. Note any Platform Designer warning or error messages and address them by modifying clock settings or verifying that a particular warning does not adversely affect your application.