AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.3.2. Early Pin Planning and I/O Assignment Analysis

HPS clock and reset I/O reside in the HPS Dedicated I/O Bank on fixed pin locations and typically share the bank with HPS peripherals such as boot flash and UART console.

GUIDELINE: Choose an I/O voltage level for the HPS Dedicated I/O.

HPS_CLK1, HPS_nPOR, and HPS_nRST are located in the HPS Dedicated I/O bank on fixed pin locations. The HPS Dedicated I/Os are LVCMOS/LVTTL supporting 1.8V, 2.5V, and 3V voltage levels. The I/O signaling voltage for this bank is established by the supply level applied to VCCIO_HPS, which can be either 1.8V, 2.5V, or 3V. Make sure the supply level chosen for VCCIO_HPS is compatible with any HPS peripheral interfaces (e.g. boot source, UART console) configured to use the HPS Dedicated I/O bank as well as board-level clock and reset circuitry for the HPS.