AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.2.1. HPS Pin Multiplexing Design Considerations

Because the HPS peripheral signals total more than the Shared I/O bank of 48 pins, the HPS component in Platform Designer offers pin multiplexing settings as well as the option to route most of the peripherals into the FPGA fabric. Any unused pins in the Shared I/O bank can be used as general purpose I/O by the FPGA in groups of 12 pins. The HPS Shared I/O resides in 3V I/O Bank 2L in the FPGA I/O column adjacent to the HPS and generally supports the full feature set of a 3V I/O bank. However, any use of the Shared I/O for HPS peripherals limits voltage level support to either 1.8V, 2.5V or 3V operation, subject to the same rules for I/O Standard compatibility and support as any other FPGA I/O bank. All peripherals connected to the I/O bank must support the selected voltage.

The Shared I/O allocated to the FPGA (in groups of 12 pins) is available to the FPGA once the device has been configured, even though HPS may still be in reset. However, if the Shared I/O has been allocated to the HPS, it is not accessible by the FPGA while the HPS is in reset. These pins can be used only by the HPS once it is out of reset.

GUIDELINE: You must route the USB, EMAC and Flash interfaces to the HPS Dedicated and Shared I/O first, starting with USB.

Intel recommends that you start by routing high speed interfaces such as USB, Ethernet, and flash to the HPS Dedicated I/O and HPS Shared I/O first. You must route USB signals to shared I/O because it is not available to the FPGA fabric. The flash boot source must be routed to the HPS dedicated I/O because these are the only I/O that are functional before the HPS Shared I/O and FPGA I/O have been configured.

GUIDELINE: Ensure that you reserve an entire quadrant of shared I/O if needed for FPGA usage.

The Shared I/O can be used by designs residing in the FPGA fabric, but the I/O must be made available on a quadrant basis (groups of 12 pins). The Shared I/O is divided into four quadrants with each quadrant being routed to either the HPS peripherals or FPGA logic, but not both. As a result, if you wish to use HPS Shared I/O for FPGA, you must reserve one of the quadrants and route the HPS peripherals to the remaining three quadrants of the shared I/O bank.

Refer to the Peripheral Pin Multiplexing tab in the HPS configuration dialog box in Platform Designer when selecting I/O Sets for peripherals. Pay attention to errors that may occur when adding peripherals. The console box at the bottom of the HPS configuration dialog box aids in resolving conflicts.