AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

4.7. Board Design Guidelines for Intel® Arria® 10 SoC FPGAs Revision History

Document Version Changes
2022.05.17 Added more information about the QSPI_SS1 pin using 1.8V QSPI flash device.
2020.08.14 Maintenance release
2019.04.17 Maintenance release
  • Removed Adapting to RGMII from the PHY Interfaces Connected through FPGA I/O section.
  • Added Connection Guidelines for Unused HPS Block section.
2017.12.20 Added the Provide Flash Memory Reset for QSPI and SD/MMC/eMMC section (previously in the Embedded Software Design Guidelines section).
2017.05.08 Added new section Using the Bootloader as a Bare-Metal Framework.
2016.09.16 Initial Release