AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.2.2. HPS I/O Settings: Constraints and Drive Strengths

GUIDELINE: Ensure that you have correctly configured the I/O settings for the HPS Shared I/O and Dedicated I/O.

The HPS pin location assignments are managed automatically when you generate the Platform Designer system containing the HPS. Likewise, timing and I/O constraints for the HPS SDRAM controller are managed by the Intel® Arria® 10 External Memory Interfaces for HPS. The only HPS I/O constraints you must manage are for the HPS Dedicated I/O and HPS Shared I/O. Constraints such as drive strength, I/O standards, and weak pull-up enables are added to the Intel® Quartus® Prime project just like FPGA constraints; and are applied to the HPS at boot time when the second stage boot loader configures the I/O. I/O constraints for dedicated I/O are stored in the device tree for the boot loader software. For HPS Shared I/O and FPGA I/O, the I/O constraints are applied to the FPGA configuration file.