AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents RMII

RMII uses a single centralized system-synchronous 50 MHz clock source (REF_CLK) for both transmit and receive paths across all ports. This simplifies system clocking and lowers pin counts in high port density systems, because your design can use a single board oscillator as opposed to per port TX_CLK/RX_CLK source synchronous clock pairs.

RMII uses two-bit wide transmit and receive datapaths. All data and control signals are synchronous to the REF_CLK rising edge. The RX_ER control signal is not used. In 10Mbps mode, all data and control signals are held valid for 10 REF_CLK clock cycles.

Figure 9. RMII MAC/PHY Interface

Interface Clocking Scheme

EMACs and RMII PHYs can provide the 50 MHz REF_CLK source. Using clock resources already present such as HPS_CLK1 input, internal PLLs further simplifies system clocking design and eliminates the need for an additional clock source.

This section discusses system design scenarios for both HPS EMAC-sourced and PHY-sourced REF_CLK.

GUIDELINE: Consult the PHY datasheet for specifics on the choice of REF_CLK source in your application.

Make sure your choice of PHY supports the REF_CLK clocking scheme in your application. Note any requirements and usage considerations specified in the PHY’s datasheet.

You can use one of the following two methods for sourcing REF_CLK:
  • HPS-Sourced REF_CLK
  • PHY-Sourced REF_CLK
Figure 10. HPS Sourced REF_CLKIn this scheme, connect the EMAC’s HPS RMII I/O TX_CLK output to both the HPS RMII I/O RX_CLK and PHY REF_CLK inputs.
Figure 11. PHY Sourced REF_CLKIn this scheme, connect the PHY’s REF_CLK output to the EMAC’s HPS RMII I/O RX_CLK input. Leave the EMAC’s HPS RMII I/O TX_CLK output unconnected. TX_CLK is always part of the HPS EMAC I/O signal set for RMII and cannot be made available as an additional Shared I/O even when not used. PHYs capable of sourcing REF_CLK are typically configured to do so through pin bootstrapping and require an external crystal or clock input to generate REF_CLK.

I/O Pin Timing

Account for routing delay differences from the REF_CLK source to REF_CLK input pins between the HPS EMAC and PHY

If RX_CLK is routed daisy-chain from source to MAC to PHY or source to PHY, you must account for the flight time difference as both REF_CLK loads will see the clock at different times.

GUIDELINE: Take into account routing delays and skews on the data and control signals to ensure meeting setup and hold as specified in the HPS SoC Device datasheet and PHY datasheet.

Signal length matching is not necessary unless you have signal lengths in excess of 24”, in which case you must perform some basic timing analysis with clock delays versus data delays.

The period is 20 ns with the 50 MHz REF_CLK and remains at this frequency regardless of whether the PHY is set to 10Mbps or 100Mbps mode.

All clocking in the HPS EMAC is based on the RX_CLK, so the Tco and PCB flight time of REF_CLK from either the EMAC or PHY can be ignored. Typical board traces up to 12 inches yield only 2 ns of flight time and Tsu of RXD to RX_CLK is 4 ns minimum, well under the 20 ns period.

There is a 2 ns hold requirement of RXD versus RX_CLK which is easily satisfied as well because the Tco of TXD with respect to RX_CLK for either the MAC or the PHY is typically over 2 ns. For Intel® Arria® 10 SoC device, the Tco of TXD with respect to RX_CLK is 7 ns to 10 ns.

GUIDELINE: Ensure the REF_CLK source meets the duty cycle requirement.

There is no jitter specification for the REF_CLK, but there is a duty cycle requirement of 35% to 65%. This requirement is met by Intel® Arria® 10 PLLs and clock outputs for GPIO or for the TX_CLK signal coming from the HPS IP specifically.

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