AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents RGMII

RGMII is the most common interface because it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer.

RGMII uses four-bit wide transmit and receive datapaths, each with its own source-synchronous clock. All transmit data and control signals are source synchronous to TX_CLK, and all receive data and control signals are source synchronous to RX_CLK.

For all speed modes, TX_CLK is sourced by the MAC, and RX_CLK is sourced by the PHY. In 1000 Mbps mode, TX_CLK and RX_CLK are 125 MHz, and Dual Data Rate (DDR) signaling is used. In 10 Mbps and 100 Mbps modes, TX_CLK and RX_CLK are 2.5 MHz and 25 MHz, respectively, and rising edge Single Data Rate (SDR) signaling is used.

Figure 12. RGMII MAC/PHY Interface

I/O Pin Timing

This section addresses RGMII interface timing from the perspective of meeting requirements in the 1000 Mbps mode. The interface timing margins are most demanding in 1000 Mbps mode, thus it is the only scenario we consider here.

At 125 MHz, the period is 8 ns, but because both edges are used, the effective period is only 4 ns. The TX and RX busses are completely separate and source synchronous, simplifying timing. The RGMII specification calls for CLK to be delayed from DATA at the receiver in either direction by a minimum 1.0 ns and a maximum 2.6 ns.

In other words, the TX_CLK must be delayed from the MAC output to the PHY input and the RX_CLK from the PHY output to the MAC input. The signals are transmitted source synchronously within the +/- 500 ps RGMII skew specification in each direction as measured at the output pins. The minimum delay needed in each direction is 1 ns but Intel® recommends to target a delay of 1.5 ns to 2.0 ns to ensure significant timing margin.

Transmit path setup/hold

Only setup and hold for TX_CLK to TX_CTL and TXD[3:0] matter for transmit. The Intel® Arria® 10 I/O can provide up to 800 ps additional delay on outputs. This delay is enabled using the output delay logic option within the assignment editor in Intel® Quartus® Prime.

GUIDELINE: For TX_CLK from the Arria 10, you must introduce at least 200 ps of delay beyond the 800 ps I/O delay to meet the 1.0 ns PHY minimum input setup time in the RGMII spec.

It is strongly recommended to increase this to HPS-provided 800 ps I/O delay plus 700 ps-1200 ps other delay for a total recommended delay of 1.5 ns to 2.0 ns. Many PHYs offer programmable skew, and some support RGMII 2.0 which defaults to skew enabled on both transmit and receive datapaths.

GUIDELINE: Between PHY delay and FPGA I/O delay features, you must ensure either 2 ns of delay to CLK versus CTL and D[3:0] or 1.2 ns typical minimum setup skew typical of most PHYs.

Consult the datasheet for your PHY vendor for more information.

GUIDELINE: Ensure your design includes the necessary Intel® settings to configure the HPS EMAC outputs for the required delays.

On the Intel® Arria® 10 SoC Development Kit and the associated Intel® Arria® 10 Golden Hardware Reference Design (the GHRD is the hardware component of the GSRD), a combination of PHY skew and FPGA skew is implemented with the Micrel PHY. Refer to the Intel® Quartus® Prime settings and PHY driver code in the Golden System Reference Design (GSRD).

Receive path setup/hold

Only setup and hold for RX_CLK to RX_CTL and RXD[3:0] are necessary to consider for receive timings. The Intel® Arria® 10 I/O can provide up to 3200 ps additional delay on inputs. For Intel® Arria® 10 inputs, the 3.2 ns I/O delay can achieve this timing for RX_CLK without any other considerations on the PHY side or board trace delay side.

GUIDELINE: Hardware developers must specify the required FPGA skew so that software developers can add the skew to the device driver code.

An example of this code is available in the Linux device driver for the Intel® Arria® 10 GSRD.