AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.5.2. Optimizing DMA Master Bandwidth through HPS Interconnect

FPGA DMA masters have access to HPS resources through the FPGA-to-HPS Bridge and FPGA-to-SDRAM ports, configurable in the HPS Platform Designer Component. The L3 and SDRAM L3 Interconnects in the HPS provide arbitration for these resources and enforce secure region and Quality of Service (QoS) settings. When planning for and designing DMA masters and related buffering that access resources through the HPS interconnect, study the architecture of the HPS interconnect and consider the following guidance and resources available for optimizing bandwidth through the interconnect.

GUIDELINE: Utilize the FPGA-to-HPS Bridge Design Example to tune for performance.

The FPGA-to-HPS Bridge Design Example is a useful platform for modeling specific data traffic access patterns between the FPGA and HPS resources. The example design includes a utility that runs on the Arm* Cortex-A9 processor in the HPS that allows selecting datapaths between endpoints, transaction characteristics (for example, burst lengths), and reporting transfer bandwidth.