AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.2. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory

One of the most important considerations when configuring the HPS is to understand how the I/O is organized in the Intel® Arria® 10 SoC devices.

Follow the guidelines for Intel® Arria® 10 SoC devices as documented in the " Intel® Arria® 10 SX Pin Connection Guidelines" section of Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines.

1. HPS Dedicated I/O

These 17 I/O are physically located inside the HPS, are dedicated for the HPS, and are primarily used for the HPS boot flash, clock, and resets. All other I/O are located in I/O columns in the FPGA logic.

2. HPS Shared I/O (shared with FPGA)

There is a single I/O bank of 48 pins (HPS shared I/O) available for either HPS peripheral signals or FPGA signals. The HPS shared I/O enters input tri-state mode when it is reset by HPS cold reset.

For more information, refer to the Booting and Configuration appendix in the Intel® Arria® 10 Hard Processor System Technical Reference Manual.

3. HPS External Memory Interface I/O (shared with FPGA)

Depending on the device and package you have selected, there are two or three modular I/O banks that can connect to SDRAM memory. One of the I/O banks is used to connect the address, command and ECC data signals. The other one or two banks are for connecting the data signals.


You can use general purpose I/O for FPGA logic, FPGA external memory interfaces and high speed serial interfaces.

The table below summarizes the characteristics of each I/O type.
Table 7.  Summary of SoC-FPGA I/O Types
  Dedicated HPS I/O HPS External Memory Interface I/O Shared HPS-FPGA IO48 FPGA I/O
Number of Available I/O 17 Up to three IO48 banks 48 All other device I/O
Location Dedicated bank of I/Os in the HPS block

I/O Banks (all banks are in the same column) 2I, 2J, 2K (adjacent to HPS)

FPGA I/O bank 2L (adjacent to HPS block) FPGA I/O banks
Voltages Supported 1.8V, 2.5V and 3.0V LVDS I/O in support of DDR3 and DDR4 protocols 3V I/O buffer type voltage support1 LVDS I/O, 3V I/O and high speed serial I/O (HSIO) buffer types voltage support2

Clock, Reset, Boot Source and UART

HPS main memory High speed HPS peripherals General purpose and transceiver I/O
Timing Constraints Fixed Provided by memory controller IP 3 Fixed for legal combinations 3 User defined
Recommended Peripherals

QSPI, NANDx8, eMMC, SD/MMC card, and UART


EMAC, USB (Refer to HPS Platform Designer Component for legal combinations)

Slow speed peripherals (I2C, SPI, EMAC-MII)

1 For details of voltage level support, see the Intel Arria 10 Core Fabric and General Purpose I/Os Handbook. HPS peripherals using shared I/O have only been characterized for 3.0V, 2.5V and 1.8V LVTTL/LVCMOS operation. All FPGA interfaces assigned to shared I/O must the compatible with HPS peripheral I/O in the same bank.
2 For details of voltage level support, see the Intel Arria 10 Core Fabric and General Purpose I/Os Handbook.
3 Note: You can access the timing information to perform off-chip analysis by reviewing the HPS timing in the Arria 10 Device Datasheet.