AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents Example 2: FPGA Writing Data into HPS SDRAM Directly

In this example, the HPS MPU requires access to data that originates from within the FPGA. For the MPU to be able to access the data coherently after it is written before the transfer starts software may need to flush or invalidate cache lines, to ensure that the SDRAM contains the latest data after it is written. Failing to perform cache operations can cause one or more cache lines to eventually become evicted overwriting the data that was written by the FPGA master.

Figure 4. FPGA Writing Data to HPS FPGA-to-SDRAM PortsFor abbreviations, refer to the figure in Overview of HPS Memory-Mapped Interfaces.

Like in Example 1, where the FPGA reads data from the FPGA-to-SDRAM ports, you can maximize write throughput into the HPS SDRAM by using two 128-bit FPGA-to-SDRAM ports with at least one master in the FPGA connected to each port.