AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents
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5.1.14. Embedded Software Debugging and Trace

GUIDELINE: It is recommended to have an available JTAG connection to the board that could be used for development as well as to debug and diagnose field issues.

This device has one JTAG port with FPGA and HPS JTAGs chained.

The HPS offers two trace interfaces either through HPS Shared I/O or FPGA I/O. The interface through HPS Shared I/O is a slow trace interface that you can use to trace low bandwidth traffic (such as the MPU operating at a low frequency). Because the interface is only a four-bit DDR interface, it provides limited bandwidth.

To improve the trace bandwidth, you can use the standard trace interface which is a 32-bit single data rate interface to the FPGA. Since trace modules typically expect trace data to be sent at a double data rate you need to convert the single data rate trace data to double data rate.

It is recommended that you instantiate the DDIO megawizard IP and set it up in output only mode to perform this conversion. The lowest 16 bits of trace data must be sent off chip first so you connect those bits to the datain_l[15:0] port of the DDIO IP.

Consult your trace vendor's datasheet to determine if the trace bus requires termination. Failure to include termination when the trace vendor requires it can lead to trace data corruption or limit the maximum operating frequency of the interface.

Figure 24. Trace Diagram