AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Public
Document Table of Contents

4.2.2. Partial Reconfiguration of the SoC FPGA

GUIDELINE: If the HPS cannot be reset to perform FPGA reconfiguration, then you must leverage the partial reconfiguration (PR) capabilities of the SoC FPGA device.

By using partial reconfiguration, you can ensure that the device I/O remain functional while a portion of the FPGA (known as a persona) is being replaced.

GUIDELINE: Ensure that you have Intel® Quartus® Prime Pro Edition because it is the only edition that supports the hierarchical design flow and generation of configuration files supporting partial reconfiguration.

It is recommended that you ensure only the hardware that needs to be replaced is located in the dynamic region of the design. This partitioning ensures that the reconfiguration time is minimized and simplifies the hardware design because less hardware must be frozen before the partial reconfiguration occurs. Freezing a partial reconfiguration region ensures that while the partial reconfiguration occurs, any outputs from the PR region are driven to a known user-defined state so that surrounding hardware is not adversely affected.

GUIDELINE: Ensure that the region undergoing partial reconfiguration is isolated with freezing logic to ensure outputs are driven to a known safe state.

GUIDELINE: Ensure that the region undergoing partial reconfiguration allows any memory accesses or data movements to complete before freezing commences.

GUIDELINE: Ensure that the region undergoing partial reconfiguration has completed configuration before it is unfrozen and data movements to and from the replaced logic commence.

If the hardware being replaced conforms to an interconnect standard such as Avalon-MM, Avalon-ST, or AXI, then during the freezing process you must also ensure that there are no outstanding memory transactions or data movements before the hardware is frozen. Freeze logic should ensure that outstanding memory transactions or data movements complete before the freezing is allowed to commence.