AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

4.5.6. NAND Flash Interface Design Guidelines

GUIDELINE: Ensure that the selected NAND flash device is an 8- or 16-bit ONFI 1.0 compliant device.

The NAND flash controller in the HPS requires:
  • The external flash device to be 8- or 16-bit ONFI 1.0 compliant
  • x8 interface for boot devices, x16 supported for mass storage (non-boot) usage
  • Single-level cell (SLC) or multi-level cell (MLC)
  • Only one ce# and rb# pin pair is available for the boot source. Up to three additional pairs are available for mass storage
  • Page size: 512 bytes, 2 KB, 4 KB or 8 KB
  • Pages per block: 32, 64, 128, 256, 384 or 512
  • Error correction code (ECC) sector size can be programmed to 512 bytes (for 4-, 8-, or 16-bit correction) or 1024 bytes (24-bit correction)
    • When the NAND device is used for booting, the boot ROM uses a 512B sector size with ECC support for up to eight correctable bits per sector.
Note: When selecting to boot from NAND, all the dedicated HPS I/O lines are used, so the UART signals (if needed) must be routed through FPGA fabric. Therefore, the UART logging is not available until the shared I/O is configured. For more information, refer o the Selecting NAND Flash Devices.

For more information, refer to the Supported Flash Devices for Arria 10 SoC web page for a list of supported NAND devices.