AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents Managing Power by Shutting Down Supplies

Lowering any of the supplies monitored by the internal POR circuitry on the SoC device (for example, the FPGA core supply (VCC) or the HPS supply (VCCL_HPS)) below their specified trip levels causes the FPGA fabric to go into a reset state.

GUIDELINE: Shutting down the FPGA core supply (VCC) effects the operation of the HPS.

When the FPGA is in POR reset, the Hard Memory Controller (HMC) I/O, Shared I/O and FPGA I/O are all in reset, resulting in the HPS losing connectivity to any external SDRAM and peripherals connected to these I/O. For the HPS to be fully operational, the FPGA supply voltages monitored by the POR circuitry must be above their POR values as described in the Arria 10 Core Fabric and General Purpose I/Os Handbook . FPGA I/O supply voltages must be at their recommended operating levels as specified in the Intel® Arria® 10 Device Data Sheet.

GUIDELINE: Shutting down the HPS voltage supply (VCCL_HPS) does not affect the FPGA core.

It is possible to shut down power to the HPS without affecting the FPGA fabric, FPGA I/O, or any Shared I/O quadrants reserved for the FPGA portion, but you must observe the power-down sequencing requirements for the HPS supplies.

For more information refer to the "Power Management in Arria 10 Devices" chapter in the Arria 10 Core Fabric and General Purpose I/Os Handbook .