AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.3. HPS Clocking and Reset Design Considerations

The main clock and resets for the HPS are HPS_CLK1, HPS_nPOR, and HPS_nRST. HPS_CLK1 (also referred to as EOSC1) is the external clock source for the HPS PLLs. The HPS PLLs generate clocks for the MPU System Complex, L3 Interconnect, HPS peripherals and HPS-to-FPGA user clocks. HPS_nPOR provides a cold reset input, and HPS_nRST provides a bidirectional warm reset resource.

This section supplements the following sections of the Arria 10 Device Design Guidelines document: “Pin Connection Considerations for Board Design” and “I/O and Clock Planning.”