AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Public
Document Table of Contents

3.3.5. HPS Reset During FPGA Reconfiguration and FPGA Configuration Failures

During FPGA reconfiguration and FPGA configuration failure, the device I/O are tri-stated, and the HPS loses access to the HPS Shared I/O and HPS External Memory Interface I/O.

GUIDELINE: Ensure that software performs an integrity check of the FPGA configuration image before initiating a FPGA configuration through the HPS.

GUIDELINE: Ensure that the HPS is in reset while the FPGA is being fully configured by an external source. This ensures the shared I/O and HPS SDRAM I/O are configured by the time those resources are needed by the HPS.

GUIDELINE: If you want to operate the HPS during reconfiguration, then design the reconfiguration bitstream as a partial reconfiguration image.

For more information, refer to the "FPGA Manager" section in the Intel® Arria® 10 Hard Processor System Technical Reference Manual.