AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents Boot Source

GUIDELINE: Determine which boot source is to be supported.

  • The HPS of the Intel® Arria® 10 SoC can be booted from a variety of sources:
    • SD/MMC Flash
    • QSPI Flash
    • NAND Flash
    • FPGA Fabric
    Note: More than one source can be supported. For example, most of the development could be done with an SD card, which is more convenient, and then the final testing and production release could target booting from QSPI.
Each possible boot source has its own considerations:
  • SD cards are cheap, universally available, and have large storage capacities. Industrial versions are available, with improved reliability. They are managed NAND flash, so wear leveling and bad block management are performed internally.
  • eMMC devices have smaller packages, are available in large capacities, and can be more reliable than SD. They are not removable, which can be a plus, allowing more rugged operation.
  • QSPI devices are very reliable, typically with a minimum of 100,000 erase cycles per sector. However they have a reduced capacity as compared to the other options. They are typically used as a boot source, but not as an application filesystem.
  • NAND devices are available in large sizes, but they are unmanaged NAND, which means that techniques such as wear leveling and bad block management must be implemented in software.
  • FPGA boot allows the HPS to boot without the need of an external Flash device. The FPGA boot memory can be synthesized out of FPGA resources (typically pre-initialized embedded memory blocks) or can be memory connected to the FPGA such as an external SRAM or SDRAM. In order to boot from the FPGA, the FPGA must be configured using a traditional configuration mechanism.