1. Overview of Design Guidelines for Intel® Arria® 10 SoC FPGAs 2. Guidelines for Interconnecting the Intel® Arria® 10 HPS and FPGA 3. Design Guidelines for HPS Portion of Arria 10 SoC FPGAs 4. Board Design Guidelines for Arria 10 SoC FPGAs 5. Embedded Software Design Guidelines for Arria 10 SoC FPGAs
1.1. SoC FPGA Designer's Checklist 1.2. Overview of HPS Design Guidelines for SoC FPGA design 1.3. Overview of Board Design Guidelines for SoC FPGA Design 1.4. Overview of Embedded Software Design Guidelines for SoC FPGA Design 1.5. Overview of Design Guidelines for Intel® Arria® 10 SoC FPGAs Revision History
3.1. Start your SoC FPGA design here 3.2. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory 3.3. HPS Clocking and Reset Design Considerations 3.4. HPS EMIF Design Considerations 3.5. DMA Considerations 3.6. Design Guidelines for HPS Portion of Intel® Arria® 10 SoC FPGAs Revision History
4.1. Power On Board Bring Up and Boot ROM/Boot Loader Debugging 4.2. FPGA Reconfiguration 4.3. HPS Power Design Considerations 4.4. Boundary Scan for HPS 4.5. Design Guidelines for HPS Interfaces 4.6. Connection Guidelines for Unused HPS Block 4.7. Board Design Guidelines for Intel® Arria® 10 SoC FPGAs Revision History
4.5.1. HPS EMAC PHY Interfaces 4.5.2. USB Interface Design Guidelines 4.5.3. QSPI Flash Interface Design Guidelines 4.5.4. SD/MMC and eMMC Card Interface Design Guidelines 4.5.5. Provide Flash Memory Reset for QSPI and SD/MMC/eMMC 4.5.6. NAND Flash Interface Design Guidelines 4.5.7. UART Interface Design Guidelines 4.5.8. I2C Interface Design Guidelines
5.1.1. Purpose 5.1.2. Assembling the components of your Software Development Platform 5.1.3. Selecting an Operating System for your application 5.1.4. Assembling your Software Development Platform for Linux 5.1.5. Assembling your Software Development Platform for a Bare-Metal Application 5.1.6. Assembling your Software Development Platform for Partner OS or RTOS 5.1.7. Choosing Boot Loader Software 5.1.8. Selecting Software Tools for Development, Debug and Trace 5.1.9. Board Bring Up Considerations 5.1.10. Boot and Configuration Design Considerations 5.1.11. Flash Device Driver Design Considerations 5.1.12. HPS ECC Design Considerations 5.1.13. Security Design Considerations 5.1.14. Embedded Software Debugging and Trace
188.8.131.52.1. Boot Source GUIDELINE: Determine which boot source is to be supported. 184.108.40.206.2. Select Desired Flash Device 220.127.116.11.3. BSEL Options 18.104.22.168.4. Boot Clock 22.214.171.124.5. Determine Boot Fuses Usage 126.96.36.199.6. CSEL Options 188.8.131.52.7. Determine Flash Programming Method 184.108.40.206.8. Selecting NAND Flash Devices 220.127.116.11.9. Selecting QSPI Flash Devices 18.104.22.168.10. Reference Materials
22.214.171.124.1. Boot Source
GUIDELINE: Determine which boot source is to be supported.
The HPS of the Intel® Arria® 10 SoC can be booted from a variety of sources:
Note: More than one source can be supported. For example, most of the development could be done with an SD card, which is more convenient, and then the final testing and production release could target booting from QSPI.
- SD/MMC Flash
- QSPI Flash
- NAND Flash
- FPGA Fabric
Each possible boot source has its own considerations:
- SD cards are cheap, universally available, and have large storage capacities. Industrial versions are available, with improved reliability. They are managed NAND flash, so wear leveling and bad block management are performed internally.
- eMMC devices have smaller packages, are available in large capacities, and can be more reliable than SD. They are not removable, which can be a plus, allowing more rugged operation.
- QSPI devices are very reliable, typically with a minimum of 100,000 erase cycles per sector. However they have a reduced capacity as compared to the other options. They are typically used as a boot source, but not as an application filesystem.
- NAND devices are available in large sizes, but they are unmanaged NAND, which means that techniques such as wear leveling and bad block management must be implemented in software.
- FPGA boot allows the HPS to boot without the need of an external Flash device. The FPGA boot memory can be synthesized out of FPGA resources (typically pre-initialized embedded memory blocks) or can be memory connected to the FPGA such as an external SRAM or SDRAM. In order to boot from the FPGA, the FPGA must be configured using a traditional configuration mechanism.
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