AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents Example 1: FPGA Reading Data from HPS SDRAM Directly

In this example, the FPGA requires access to data that is stored in the HPS SDRAM. For the FPGA to access the same copy of the data as the MPU has access to, the L1 data cache and L2 cache need to be flushed if they already have a copy of the data. Once the HPS SDRAM contains the most up-to-date copy of the data, the optimal path for the FPGA to access this data is for FPGA masters to read the data through a FPGA-to-SDRAM port.

Figure 3. FPGA Reading Data from HPS FPGA-to-SDRAM PortsFor abbreviations, refer to the figure in Overview of HPS Memory-Mapped Interfaces.

Since the Arria 10 HPS offers two 128-bit ports into the SDRAM, you can maximize the read throughput by implementing two masters in the FPGA accessing data in the SDRAM through both ports. If you decide to implement multiple paths into the SDRAM through the FPGA-to-SDRAM ports, ensure that you handle synchronization at a system level since each port is serviced independently from the other. If one port should have a higher priority than the other, then you can adjust the QoS settings for each port shaping the traffic patterns as needed by your application. It is recommended to use a burst capable master in the FPGA to read from the FPGA-to-SDRAM ports, capable of posting burst lengths of four beats or larger.