AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

3.4.4. HPS Memory Debug

GUIDELINE: Verify the memory interface is operational using an FPGA EMIF and the external memory tool kit.

Because the HPS SDRAM controller does not support the external memory interface toolkit, verify that the memory interface is operational using the non-HPS memory controller first. Create a design that instantiates the FPGA memory controller and routes it to the same I/O that the HPS memory controller uses. Once you have verified that the interface is operational with the EMIF toolkit, ensure that you properly instantiate the Arria 10 External Memory Interfaces for HPS IP as described in the sub-section on Instantiating the Arria 10 HPS EMIF IP described in the "Considerations for Connecting HPS to SDRAM" section.

Refer to External Memory Interfaces in Arria 10 Devices, External Memory Interface Handbook, and Arria 10 External Memory Interface Pin Interface for additional information.