AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Public
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Document Table of Contents

1. Overview of Design Guidelines for Intel® Arria® 10 SoC FPGAs

Updated for:
Intel® Quartus® Prime Design Suite 18.1

This document provides a set of guidelines and recommendations, as well as a list of factors to consider, for designs that use the Intel® Arria® 10 SoC FPGA devices. This document assists you in the planning and early design phases of the Intel® Arria® 10 SoC FPGA design, Platform Designer sub-system design, board design and software application design.

This application note does not include all the Intel® Arria® 10 Hard Processor System (HPS) device details, features or information on designing the hardware or software system. For more information about the Intel® Arria® 10 HPS features and individual peripherals, refer to the Intel® Arria® 10 Hard Processor System Technical Reference Manual.

Note:

Intel recommends that you use Intel® Quartus® Prime Pro Edition and SoC EDS Professional Edition to develop Intel® Arria® 10 designs. Although Intel® Quartus® Prime Standard Edition and SoC EDS Standard Edition continue to support the Intel® Arria® 10 SoC family on a maintenance basis. For future enhancements, use the supported software Intel® Quartus® Prime Pro Edition and SoC EDS Professional Edition.

Hardware developed with Intel® Quartus® Prime Pro Edition only supports software developed with the SoC EDS Professional Edition. Hardware developed with Intel® Quartus® Prime Standard Edition only supports software developed with SoC EDS Standard Edition.

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